The present disclosure relates generally to information handling systems (IHSs), and more particularly to providing memory sparing in an IHS independent of a memory controller.
As the value and use of information continues to increase, individuals and businesses seek additional ways to process and store information. One option is an IHS. An IHS generally processes, compiles, stores, and/or communicates information or data for business, personal, or other purposes. Because technology and information handling needs and requirements may vary between different applications, IHSs may also vary regarding what information is handled, how the information is handled, how much information is processed, stored, or communicated, and how quickly and efficiently the information may be processed, stored, or communicated. The variations in IHSs allow for IHSs to be general or configured for a specific user or specific use such as financial transaction processing, airline reservations, enterprise data storage, or global communications. In addition, IHSs may include a variety of hardware and software components that may be configured to process, store, and communicate information and may include one or more computer systems, data storage systems, and networking systems.
Currently, it is common for an IHS that handles critical data to hold a region of memory in reserve (i.e. a ‘spare’ region such as, for example, a spare rank) to replace an active region of memory that develops unrecoverable or excessive recoverable errors. This is typically referred to as memory sparing. However, current systems for memory sparing have weaknesses that reduce their desirability. For instance, memory sparing may not be available on all processor types (e.g., lower cost processors). In addition, memory sparing may require a uniform population of DIMMs across the IHS, which limits the ability to create different levels of protection based on memory regions. Further, memory sparing is traditionally controlled by a memory controller in the IHS. Conventional memory controller controlled memory sparing systems create memory sparing associations based only on the regions of memory visible to the memory controller. However, in some IHSs the partitioning of physical memory regions (e.g., the physical ranks on buffered DIMMs and risers such as Load-Reduced Dual In-line Memory Modules (LRDIMMs) and 3D Through-Silicon Via (TSV) DIMMs) may be hidden from the memory controller, and thus those memory regions are excluded from the memory sparing system. Even further, memory sparing is not generally supported with other Reliability/Availability/Serviceability (RAS) features such as mirroring or lockstep. Finally, in conventional memory sparing systems controlled by the memory controller, when an active rank fails, system operations may be interrupted until the memory controller copies data from the active rank to a spare rank.
Therefore, what is needed in an improved memory sparing system.